1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) output buffer circuit for use in a semiconductor device, more particularly to a CMOS output buffer circuit having improved power and ground noise characteristics.
2. Description of the Related Art
As the operating frequencies of semiconductor devices have increased, the output switching speeds thereof have also increased, which translates into reduced rise/fall times and pulse widths. Also, any increase in output switching speed increases the rate of change of the switching current. Due to chip-package interface power distribution parasitics, switching noise is created when output buffer circuits switch simultaneously.
FIG. 1 is a circuit diagram showing a conventional CMOS output buffer circuit. Referring to FIG. 1, the output buffer 100 is composed of two CMOS inverter stages 110 and 120 connected in series between an input terminal 101 and an output terminal 102. A data signal from an internal circuit of the semiconductor chip is applied to the input terminal 101. A CMOS inverter circuit 110 of a first stage comprises a P-channel MOS transistor MP11 and an N-channel MOS transistor MN11. Gates of the transistors MP11 and MN11 are connected to the input terminal 101 and drains thereof are connected to each other. Sources of the transistors MP11 and MN11 are connected to a power supply potential V.sub.DD and a ground potential V.sub.SS, respectively.
Also, a CMOS inverter circuit 120 of a second stage comprises a P-channel MOS transistor MP12 and an N-channel MOS transistor MN12. Gates of the transistors MP12 and MN12 are connected to the drains of the transistors MP11 and MN11, and drains thereof are connected to the output terminal 102. Sources of the transistors MP12 and MN12 are connected to the power supply potential V.sub.DD and the ground potential V.sub.SS, respectively.
Since a semiconductor chip of a semiconductor device is generally packaged, the output buffer circuit included in the semiconductor chip is connected to an external circuit by means of a lead frame. It is assumed that the lead frame has an inductance `L` and the switching time of the output buffer is `t`. If a current `I`, which flows through transistor MP12 or MN12, varies, noise voltage `V.sub.N ` is generated at the output terminal 102 at a rate expressed by the following formula. ##EQU1## In formula (1), di/dt denotes a variation in the current `I` with respect to time.
In the above arrangement, since in general the output buffer should drive a large amount of current, as shown in FIG. 6B, a peak noise caused by a spike of switching current occurs on the output terminal of the buffer at the beginning of the switching operation or when the voltage of the output terminal starts to change. The switching noise is generated by an increase in the current flowing to a power supply terminal to charge a parasitic capacitive load at the output terminal of the buffer.
Therefore, in order to design a semiconductor device of high speed and reliability, it is essential that at any given arbitrary time the switching noise must be limited to within a maximum allowable noise level. Unless power and ground noises are controlled, reliable operation of logic circuits that are connected to the same power supply potential V.sub.DD and ground potential V.sub.SS can not be guaranteed. Some of the problems associated with switching noise induced operational errors include 1) false triggering, 2) double clocking, and/or 3) missing clocked pulses.